Inaccurate alignment during chip stacking leads to misaligned interconnects between top and bottom chips and therefore less reliable bonding quality which thereby decreases data flow within the stacked chips. IC chips are stacked onto a base substrate or onto other IC's in a stack by robotic pick-and-place method, either on a chip per chip basis or by attaching multiple chips to a carrier and placing the chips onto a base substrate. In either of these techniques, it is known that self-alignment of individual chips with respect to their intended location on the base substrate or on a previously deposited chip can be applied. This is obtained by making the surfaces that are to face each other hydrophilic and introducing a drop of water between the surfaces as the chip is placed. Self-alignment is established through capillary force which results from surface tension of the fluid in the water-filled space between the two components. Once the two surfaces are aligned, the electrical bond between the microbumps of the components can be accomplished by thermocompression, direct bonding or reflow techniques, the fluid between the components being evaporated by heating the assembly or by letting the assembly dry at room temperature.
These techniques suffer from a number of inaccuracies in terms of a correct alignment. Alignment is not consistent for multiple chips placed throughout the same wafer. During bonding, alignment is likely to become lost especially when thermocompression is used. Finally, as the size and thus the weight of individual ICs decreases, for instance by backgrinding, the surface tension based alignment fails to align the ICs correctly as the weight is not enough to develop a capillary force for self-alignment. Also, when the thickness of the ICs decreases, warping of the ICs is likely to occur due to internal strain of different layers. These above-mentioned factors contribute to the overall misalignment.